1. Field of the Invention
This invention relates to the fabrication of an improved MOS device on an integrated circuit substrate. More particularly, this invention relates to the production of at least one MOS transistor on a substrate using self aligned raised polysilicon contacts for at least some of the electrodes with metal silicide surfaces thereon to promote conductivity.
2. Description of the Prior Art
MOS devices are usually constructed in a non planarized fashion with steps created when making contact with the source and drain regions which are lower than the gate region. Also, despite the high density of the MOS devices, the gate contact usually occupies a large area due to the need to make the contact in a position offset to the gate region because of alignment problems.
Furthermore, in the construction of MOS devices, the source and drain junctions may be formed too deep causing the junctions to sometimes extend under the gate region causing overlap capacitance which degrades the performance of the device. The extension of the junction under the gate may be caused by forming the junction too deeply in the substrate. This can also cause the depletion region to extend sideways into the channel causing a short channel effect which further degrades the performance and functionality as well as long term reliability. If the source and drain regions can be formed as shallow junctions, which do not extend laterally, e.g., beneath the gate, the junction capacitance may also be lowered because of the reduction in the junction area.
In our prior U.S. patent application Ser. No. 747,517, filed June, 21, 1985, and entitled FAST BIPOLAR TRANSISTOR FOR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MAKING SAME, cross reference to which is hereby made, we described and claimed a structure having raised polysilicon emitter and collector contacts with oxide spacers on the sidewalls and a metal silicide conductive path on the surface between the base contact and a point adjacent the oxide spacer on the sidewall of the emitter to provide a faster device with higher gain and lower capacitance and resistance. In one embodiment in that application, the provision of a raised base electrode is also disclosed which provides an advantage in planarization which results from forming all of the contacts in approximately the same plane by the raising of the base contact.
It would be very desirable to be able to fabricate one or more MOS devices on the same substrate in a manner which would address the problems discussed above.